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AD5025/45/65
Preliminary Technical Data
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2. See Figure 3 and
Figure 5. V
DD
= 2.7 V to 5.5 V. All specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 4.
Limit at T
MIN
, T
MAX
V
DD
= 2.7 V to 5.5 V
Unit
t
11
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
8
t
9
t
10
t
11
t
12
t
13
t
14
t
15
t
162, 3
t
173
t
183
t
193
t
20
20
ns min
Parameter
Conditions/Comments
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge set-up time
Data set-up time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time (single channel update)
Minimum SYNC high time ( all channel update)
SYNC rising edge to SCLK fall ignore
SCLK falling edge to SYNC fall ignore
LDAC pulse width low
SCLK falling edge to LDAC rising edge
CLR pulse width low
SCLK falling edge to LDAC falling edge
CLR pulse activation time
SCLK rising edge to SDO valid
SCLK falling edge to SYNC rising edge
SYNC rising edge to SCLK rising edge
SYNC rising edge to LDAC falling edge
PDL pulse width activation time
20
10
10
16.5
5
5
0
1.9
10.5
16.5
0
20
20
10
10
10.6
22
5
8
0
ns min
ns min
ns min
ns min
ns min
ns min
ns min
us min
us min
ns min
ns min
ns min
ns min
ns min
ns min
us min
ns max
ns min
ns min
ns min
1
Maximum SCLK frequency is 50 MHz at V
DD
= 2.7 V to 5.5 V. Guaranteed by design and characterization; not production tested.
2
Measured with the load circuit of Figure 16. t
16
determines the maximum SCLK frequency in daisy-chain mode.
3
Daisy-chain mode only.
2mA
I
OL
2mA
I
OH
V
OH
(MIN)
TO OUTPUT
PIN
C
L
50pF
0
Figure 2. Load Circuit for Digital Output (SDO) Timing Specifications
Rev. PrB | Page 6 of 3
3
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